EP20K30ETC144-2N Datasheet, PDF (45/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Figure 29. APEX 20KE I/O Banks
I/O Bank 1
I/O Bank 2
I/O Bank 8
LVDS/LVPECL
Output
Block (2)
(1)
I/O Bank 7
Regular I/O Blocks Support
■ LVTTL
■ LVCMOS
■ 2.5 V
■ 1.8 V
■ 3.3 V PCI
■ LVPECL
■ HSTL Class I
■ GTL+
■ SSTL-2 Class I and II
■ SSTL-3 Class I and II
■ CTT
■ AGP
Individual
Power Bus
I/O Bank 3
(1)
LVDS/LVPECL
Input
Block (2)
I/O Bank 4
I/O Bank 6
I/O Bank 5
Notes to Figure 29:
(1) For more information on placing I/O pins in LVDS blocks, refer to the Guidelines for
Using LVDS Blocks section in Application Note 120 (Using LVDS in APEX 20KE
Devices).
(2) If the LVDS input and output blocks are not used for LVDS, they can support all of
the I/O standards and can be used as input, output, or bidirectional pins with
V_CCIO set to 3.3 V, 2.5 V, or 1.8 V.
Power Sequencing & Hot Socketing
Because APEX 20K and APEX 20KE devices can be used in a mixed-
voltage environment, they have been designed specifically to tolerate any
possible power-up sequence. Therefore, the V_CCIO and V_CCINT power
supplies may be powered in any order.
f
For more information, please refer to the “Power Sequencing
Considerations” section in the Configuring APEX 20KE & APEX 20KC
Devices chapter of the Configuration Devices Handbook.
Signals can be driven into APEX 20K devices before and during power-up
without damaging the device. In addition, APEX 20K devices do not drive
out during power-up. Once operating conditions are reached and the
device is configured, APEX 20K and APEX 20KE devices operate as
specified by the user.
Altera Corporation
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