EP20K30ETC144-2N Datasheet, PDF (12/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Each LAB contains dedicated logic for driving control signals to its LEs
and ESBs. The control signals include clock, clock enable, asynchronous
clear, asynchronous preset, asynchronous load, synchronous clear, and
synchronous load signals. A maximum of six control signals can be used
at a time. Although synchronous load and clear signals are generally used
when implementing counters, they can also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked (e.g., any LE in a particular LAB
using CLK1 will also use CLKENA1). LEs with the same clock but different
clock enable signals either use both clock signals in one LAB or are placed
into separate LABs.
If both the rising and falling edges of a clock are used in a LAB, both LAB-
wide clock signals are used.
The LAB-wide control signals can be generated from the LAB local
interconnect, global signals, and dedicated clock pins. The inherent low
skew of the FastTrack Interconnect enables it to be used for clock
distribution. Figure 4 shows the LAB control signal generation circuit.
Figure 4. LAB Control Signal Generation
Dedicated
Clocks
2 or 4 (1)
Global
4
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
SYNCLOAD
or LABCLKENA2
LABCLKENA1
LABCLR1 (2)
SYNCCLR
or LABCLK2 (3)
LABCLK1
LABCLR2 (2)
Notes to Figure 4:
(1) APEX 20KE devices have four dedicated clocks.
(2) The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the
LAB.
(3) The SYNCCLR signal can be generated by the local interconnect or global signals.
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