EP20K30ETC144-2N Datasheet, PDF (75/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 36. APEX 20KE Routing Timing Microparameters Note (1)
Symbol
Parameter
t_F1-4
t_F5-20
t_F20+
Fanout delay using Local Interconnect
Fanout delay estimate using MegaLab Interconnect
Fanout delay estimate using FastTrack Interconnect
Note to Table 36:
(1) These parameters are worst-case values for typical applications. Post-compilation
timing simulation and timing analysis are required to determine actual worst-case
performance.
Table 37. APEX 20KE Functional Timing Microparameters
Symbol
TCH
TCL
TCLRP
TPREP
TESBCH
TESBCL
TESBWP
TESBRP
Parameter
Minimum clock high time from clock pin
Minimum clock low time from clock pin
LE clear Pulse Width
LE preset pulse width
Clock high time for ESB
Clock low time for ESB
Write pulse width
Read pulse width
Tables 38 and 39 describe the APEX 20KE external timing parameters.
Table 38. APEX 20KE External Timing Parameters Note (1)
Symbol
t_INSU
t_INH
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
Clock Parameter
Setup time with global clock at IOE input register
Hold time with global clock at IOE input register
Clock-to-output delay with global clock at IOE output register
Setup time with PLL clock at IOE input register
Hold time with PLL clock at IOE input register
Clock-to-output delay with PLL clock at IOE output register
Conditions
C1 = 10 pF
C1 = 10 pF
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