EP20K30ETC144-2N Datasheet, PDF (87/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 57. EP20K60E f_MAX Routing Delays
Symbol
-1
t_F1-4
t_F5-20
t_F20+
Min
Max
0.24
1.45
1.96
-2
Min
Max
0.26
1.58
2.14
-3
Unit
Min
Max
0.30
ns
1.79
ns
2.45
ns
Table 58. EP20K60E Minimum Pulse Width Timing Parameters
Symbol
t_CH
t_CL
t_CLRP
t_PREP
t_ESBCH
t_ESBCL
t_ESBWP
t_ESBRP
-1
Min
Max
2.00
2.00
0.20
0.20
2.00
2.00
1.29
1.04
-2
Min
Max
2.50
2.50
0.28
0.28
2.50
2.50
1.80
1.45
-3
Unit
Min
Max
2.75
ns
2.75
ns
0.41
ns
0.41
ns
2.75
ns
2.75
ns
2.66
ns
2.14
ns
Table 59. EP20K60E External Timing Parameters
Symbol
t_{I N S U}
t_{I N H}
t_{O U T C O}
t_{I N S U P L L}
t_{I N H P L L}
t_{O U T C O P L L}
-1
Min
Max
2.03
0.00
2.00
4.84
1.12
0.00
0.50
3.37
-2
Min
Max
2.12
0.00
2.00
5.31
1.15
0.00
0.50
3.69
-3
Unit
Min
Max
2.23
ns
0.00
ns
2.00
5.81
ns
-
ns
-
ns
-
-
ns
Altera Corporation
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