EP20K30ETC144-2N Datasheet, PDF (4/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
– Altera MegaCore^® functions and Altera Megafunction Partners
Program (AMPP^SM) megafunctions
– NativeLink^TM integration with popular synthesis, simulation,
and timing analysis tools
– Quartus II SignalTap^® embedded logic analyzer simplifies
in-system design evaluation by giving access to internal nodes
during device operation
– Supports popular revision-control software packages including
PVCS, Revision Control System (RCS), and Source Code Control
System (SCCS )
Table 4. APEX 20K QFP, BGA & PGA Package Options & I/O Count Notes (1), (2)
Device
EP20K30E
EP20K60E
EP20K100
EP20K100E
EP20K160E
EP20K200
EP20K200E
EP20K300E
EP20K400
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
144-Pin
TQFP
92
92
101
92
88
208-Pin
PQFP
RQFP
125
148
159
151
143
144
136
240-Pin
PQFP
RQFP
356-Pin BGA 652-Pin BGA 655-Pin PGA
151
196
189
252
183
246
175
271
174
277
168
271
376
152
408
502
502
488
488
488
488
4
Altera Corporation