EP20K30ETC144-2N Datasheet, PDF (114/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
SRAM configuration elements allow APEX 20K devices to be
reconfigured in-circuit by loading new configuration data into the
device. Real-time reconfiguration is performed by forcing the device
into command mode with a device pin, loading different
configuration data, reinitializing the device, and resuming user-
mode operation. In-field upgrades can be performed by distributing
new configuration files.
Configuration Schemes
The configuration data for an APEX 20K device can be loaded with
one of five configuration schemes (see Table 111), chosen on the basis
of the target application. An EPC2 or EPC16 configuration device,
intelligent controller, or the JTAG port can be used to control the
configuration of an APEX 20K device. When a configuration device
is used, the system can configure automatically at system power-up.
Multiple APEX 20K devices can be configured in any of five
configuration schemes by connecting the configuration enable (nCE)
and configuration enable output (nCEO) pins on each device.
Table 111. Data Sources for Configuration
Configuration Scheme
Configuration device
Passive serial (PS)
Passive parallel asynchronous (PPA)
Passive parallel synchronous (PPS)
JTAG
Data Source
EPC1, EPC2, EPC16 configuration devices
MasterBlaster or ByteBlasterMV download cable or serial data source
Parallel data source
Parallel data source
MasterBlaster or ByteBlasterMV download cable or a microprocessor
with a Jam or JBC File
f
Device Pin-Outs
For more information on configuration, see Application Note 116
(Configuring APEX 20K, FLEX 10K, & FLEX 6000 Devices.)
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin-out information
114
Altera Corporation