EP1S40F780C7 Datasheet, PDF (773/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Configuring Stratix & Stratix GX Devices
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 5 of 8)
Pin Name
nCEO
User Mode
N/A
Configuration
Scheme
Pin Type
All Multi-
Device
Schemes
Output
Description
Output that drives low when device
configuration is complete. In single device
configuration, this pin is left floating. In multi-
device configuration, this pin feeds the next
device’s nCE pin. The nCEO of the last device
in the chain is left floating.
The voltage levels driven out by this pin are
dependent on the V_{C C I O} of the I/O bank it
resides in.
DCLK
N/A
Synchronous Input
In PS and FPP configuration, DCLK is the clock
configuration (PS, FPP) input used to clock data from an external
schemes
source into the target device. Data is latched
(PS, FPP)
into the FPGA on the rising edge of DCLK.
In PPA mode, DCLK should be tied high to V_{C C}
to prevent this pin from floating.
DATA0
I/O
PS, FPP, PPA Input
After configuration, this pin is tri-stated. In
schemes that use a configuration device,
DCLK is driven low after configuration is done.
In schemes that use a control host, DCLK
should be driven either high or low, whichever
is more convenient. Toggling this pin after
configuration does not affect the configured
device. This pin uses Schmitt trigger input
buffers.
Data input. In serial configuration modes, bit-
wide configuration data is presented to the
target device on the DATA0 pin. The V_IH and
V_{I L} levels for this pin are dependent on the
V_{C CI O} of the I/O bank that it resides in.
After configuration, DATA0 is available as a
user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
After configuration, EPC1 and EPC1441
devices tri-state this pin, while enhanced
configuration and EPC2 devices drive this pin
high.
Altera Corporation
July 2005
11–55
Stratix Device Handbook, Volume 2