EP1S40F780C7 Datasheet, PDF (227/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

DC & Switching Characteristics
Table 4–77. EP1S30 External I/O Timing on Row Pins Using Regional Clock Networks
Parameter
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Min
Max
-8 Speed Grade
Unit
Min
Max
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_INSUPLL
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
2.322
2.467
2.828
3.342
ns
0.000
0.000
0.000
0.000
ns
2.731 5.408 2.731 5.843 2.731 6.360 2.731 7.036
ns
2.758 5.462 2.758 5.899 2.758 6.428 2.758 7.118
ns
2.758 5.462 2.758 5.899 2.758 6.428 2.758 7.118
ns
1.291
1.283
1.469
1.832
ns
0.000
0.000
0.000
0.000
ns
1.192 2.539 1.192 2.737 1.192 2.786 1.192 2.742
ns
1.219 2.539 1.219 2.793 1.219 2.854 1.219 2.824
ns
1.219 2.539 1.219 2.793 1.219 2.854 1.219 2.824
ns
Table 4–78. EP1S30 External I/O Timing on Row Pins Using Global Clock Networks
Parameter
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Min
Max
-8 Speed Grade
Unit
Min
Max
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_INSUPLL
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
1.995
2.089
2.398
2.830
ns
0.000
0.000
0.000
0.000
ns
2.917 5.735 2.917 6.221 2.917 6.790 2.917 7.548
ns
2.944 5.789 2.944 6.277 2.944 6.858 2.944 7.630
ns
2.944 5.789 2.944 6.277 2.944 6.858 2.944 7.630
ns
1.337
1.312
1.508
1.902
ns
0.000
0.000
0.000
0.000
ns
1.164 2.493 1.164 2.708 1.164 2.747 1.164 2.672
ns
1.191 2.547 1.191 2.764 1.191 2.815 1.191 2.754
ns
1.191 2.547 1.191 2.764 1.191 2.815 1.191 2.754
ns
Altera Corporation
January 2006
4–47
Stratix Device Handbook, Volume 1