EP1S40F780C7 Datasheet, PDF (137/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Figure 2–66. Input Timing Diagram in DDR Mode
Data at
input pin
A0 B1 A1 B2 A2 B3 A3 B4
CLK
A'
Input To
Logic Array
B'
A1
A2
A3
B1
B2
B3
Stratix Architecture
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from LEs on rising clock edges. These
output registers are multiplexed by the clock to drive the output pin at a
×2 rate. One output register clocks the first bit out on the clock high time,
while the other output register clocks the second bit out on the clock low
time. Figure 2–67 shows the IOE configured for DDR output. Figure 2–68
shows the DDR output timing diagram.
Altera Corporation
July 2005
2–113
Stratix Device Handbook, Volume 1