EP1S40F780C7 Datasheet, PDF (105/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Stratix Architecture
Figure 2–48. EP1S30, EP1S40, EP1S60, EP1S80 Device I/O Clock Groups
IO_CLKA[7:0]
IO_CLKB[7:0]
IO_CLKC[7:0]
IO_CLKD[7:0]
8
8
8
8
I/O Clock Regions
8
IO_CLKP[7:0]
8
IO_CLKO[7:0]
22 Clocks in the 22 Clocks in the 22 Clocks in the 22 Clocks in the
Half-Quadrant Half-Quadrant Half-Quadrant
Half-Quadrant
8
IO_CLKE[7:0]
8
IO_CLKF[7:0]
8
IO_CLKN[7:0]
8
IO_CLKM[7:0]
22 Clocks in the 22 Clocks in the 22 Clocks in the 22 Clocks in the
Half-Quadrant Half-Quadrant Half-Quadrant
Half-Quadrant
8
IO_CLKG[7:0]
8
IO_CLKH[7:0]
8
8
8
8
IO_CLKL[7:0]
IO_CLKK[7:0]
IO_CLKJ[7:0]
IO_CLKI[7:0]
You can use the Quartus II software to control whether a clock input pin
is either global, regional, or fast regional. The Quartus II software
automatically selects the clocking resources if not specified.
Enhanced & Fast PLLs
Stratix devices provide robust clock management and synthesis using up
to four enhanced PLLs and eight fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock-
frequency synthesis. With features such as clock switchover, spread
spectrum clocking, programmable bandwidth, phase and delay control,
and PLL reconfiguration, the Stratix device’s enhanced PLLs provide you
with complete control of your clocks and system timing. The fast PLLs
Altera Corporation
July 2005
2–81
Stratix Device Handbook, Volume 1