EP1S40F780C7 Datasheet, PDF (400/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

External Memory Standards
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Figure 3–3 shows DDR SDRAM interfacing from the I/O through the
dedicated circuitry to the logic array. When the DQS pin acts as an input
strobe, the dedicated circuitry shifts the incoming DQS pin by either 72°
or 90° and clocks the DDR input registers. Because of the DDR input
registers architecture in Stratix and Stratix GX devices, the shifted DQS
signal must be inverted. The DDR registers outputs are sent to two LE
registers to be synchronized with the system clock.
Refer to the DC & Switching Characteristics chapter in volume 1 of the
Stratix Device Handbook for frequency limits regarding the 72 and 90°
phase shift for DQS.
Figure 3–3. DDR SDRAM Interfacing
DQS
Compensated
Delay Shift
User logic/ ²
OE
DDR
OE
GND
DDR
Output
Registers
Registers
OE
DDR
OE
Δt
Registers
PLL _{− 90˚}
DQS Bus
DQ
2
DDR
Output
Registers
2
DDR
Input
Registers
I/O Elements &
Periphery
LE
Register
Resynchronizing
Global Clock
LE
Register
Adjacent LAB LEs
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For more information on DDR SDRAM specifications, see JEDEC
standard publications JESD79C from www.jedec.org, or see
AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices.
RLDRAM II
RLDRAM II provides fast random access as well as high bandwidth and
high density, making this memory technology ideal for high-speed
network and communication data storage applications. The fast random
access speeds in RLDRAM II devices make them a viable alternative to
SRAM devices at a lower cost. Additionally, RLDRAM II devices have
minimal latency to support designs that require fast response times.
3–4
Stratix Device Handbook, Volume 2
Altera Corporation
June 2006