EP1S40F780C7 Datasheet, PDF (505/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

High-Speed Differential I/O Interfaces in Stratix Devices
Table 5–6. High-Speed Timing Specifications & Terminology (Part 2 of 2)
High-Speed Timing Specification
t_FALL
Timing unit interval (TUI)
f_HSDR
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak)
Output jitter (peak-to-peak)
t_DUTY
t_LOCK
Terminology
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t_C/w).
Maximum LVDS data transfer rate (f_HSDR = 1/TUI).
The timing difference between the fastest and slowest output edges,
including t_CO variation and clock skew. The clock is included in the TCCS
measurement.
The period of time during which the data must be valid in order for you to
capture it correctly. The setup and hold times determine the ideal strobe
position within the sampling window.
SW = t_SW (max) – t_SW (min).
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Altera Corporation
July 2005
5–33
Stratix Device Handbook, Volume 2