EP1S40F780C7 Datasheet, PDF (169/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Configuration & Testing
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1 Stratix, Stratix II, Cyclone^®, and Cyclone II devices must be
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix, Stratix II,
Cyclone, and Cyclone II devices are in the 18th or after they will
fail configuration. This does not affect SignalTap II.
For more information on JTAG, see the following documents:
■ AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices
■ Jam Programming & Test Language Specification
SignalTap II
Embedded Logic
Analyzer
Stratix devices feature the SignalTap II embedded logic analyzer, which
monitors design operation over a period of time through the IEEE Std.
1149.1 (JTAG) circuitry. You can analyze internal logic at speed without
bringing internal signals to the I/O pins. This feature is particularly
important for advanced packages, such as FineLine BGA^® packages,
because it can be difficult to add a connection to a pin during the
debugging process after a board is designed and manufactured.
Configuration
The logic, circuitry, and interconnects in the Stratix architecture are
configured with CMOS SRAM elements. Altera^® devices are
reconfigurable. Because every device is tested with a high-coverage
production test program, you do not have to perform fault testing and can
focus on simulation and design verification.
Stratix devices are configured at system power-up with data stored in an
Altera serial configuration device or provided by a system controller.
Altera offers in-system programmability (ISP)-capable configuration
devices that configure Stratix devices via a serial data stream. Stratix
devices can be configured in under 100 ms using 8-bit parallel data at
100 MHz. The Stratix device’s optimized interface allows
microprocessors to configure it serially or in parallel, and synchronously
or asynchronously. The interface also enables microprocessors to treat
Stratix devices as memory and configure them by writing to a virtual
memory location, making reconfiguration easy. After a Stratix device has
been configured, it can be reconfigured in-circuit by resetting the device
and loading new data. Real-time changes can be made during system
operation, enabling innovative reconfigurable computing applications.
Operating Modes
The Stratix architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
Altera Corporation
July 2005
3–5
Stratix Device Handbook, Volume 1