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EP1S40F780C7 Datasheet, PDF (60/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1 | |||
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TriMatrix Memory
Table 2â11. M-RAM Combined Byte Selection for Ã144 Mode Notes (1), (2)
byteena[15..0]
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
[8] = 1
[9] = 1
[10] = 1
[11] = 1
[12] = 1
[13] = 1
[14] = 1
[15] = 1
datain Ã144
[8..0]
[17..9]
[26..18]
[35..27]
[44..36]
[53..45]
[62..54]
[71..63]
[80..72]
[89..81]
[98..90]
[107..99]
[116..108]
[125..117]
[134..126]
[143..135]
Notes to Tables 2â10 and 2â11:
(1) Any combination of byte enables is possible.
(2) Byte enables can be used in the same manner with 8-bit words, i.e., in à 16, à 32,
à 64, and à 128 modes.
Similar to all RAM blocks, M-RAM blocks can have different clocks on
their inputs and outputs. All input registersârenwe, datain, address,
and byte enable registersâare clocked together from either of the two
clocks feeding the block. The output register can be bypassed. The eight
labclk signals or local interconnect can drive the control signals for the
A and B ports of the M-RAM block. LEs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals as shown in Figure 2â19.
2â36
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
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