EP1S40F780C7 Datasheet, PDF (350/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Clocking
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. All resources within the device—IOEs, LEs, DSP blocks, and
all memory blocks—can use the global clock networks as clock sources.
These resources can also be used for control signals, such as clock enables
and synchronous or asynchronous clears fed from the external pin.
Internal logic can also drive the global clock networks for internally
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout. Figure 1–19 shows the 16 dedicated CLK
pins driving global clock networks.
Figure 1–19. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
Global Clock [15..0] ^CLK[11..8]
CLK[7..4]
Regional Clock Network
There are four regional clock networks within each quadrant of the
Stratix or Stratix GX device that are driven by the same dedicated
CLK[15..0] input pins or from PLL outputs. From a top view of the
silicon, RCLK[0..3] are in the top-left quadrant, RCLK[8..11] are in
the top-right quadrant, RCLK[4..7] are in the bottom-left quadrant, and
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Stratix Device Handbook, Volume 2
Altera Corporation
July 2005