EP1S40F780C7 Datasheet, PDF (536/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Software Support
Data Realignment
Check the Use the “rx_data_align” input port box within the Input Ports
box to add the rx_data_align output port and enable the data
realignment circuitry in Stratix SERDES. See “Receiver Data
Realignment” on page 5–25 for more information. If necessary, you can
create a state machine to send a pulse to the rx_data_align port to
realign the data coming in the LVDS receiver. You need to assert the port
for at least two clock cycles to enable the data realignment circuitry. Go
to the Altera web site at www.altera.com for a sample design written in
Verilog HDL.
For guaranteed performance when using data realignment, check the
Add Extra registers for rx_data_align input box when using the
rx_data_align port. The Quartus II software places one
synchronization register in the LE closest to the rx_data_align port.
Register Outputs
Check the Register outputs box to register the receiver’s output data. The
register acts as the module’s register boundary. If the module fed by the
receiver does not have a register boundary for the data, turn this option
on. The number of registers used is proportional to the deserialization
factor (J). The Quartus II software places the synchronization registers in
the LEs closest to the SERDES circuitry.
Use Common PLL for Both Transmitter & Receiver
Check the Use Common PLLs for Rx and Tx box to place both the LVDS
transmitter and the LVDS receiver in the same Stratix device I/O bank.
The Quartus II software allows the transmitter and receiver to share the
same fast PLL when they use the same input clock. Although you must
separate the transmitter and receiver modules in your design, the
Quartus II software merges the fast PLLs when appropriate and give you
the following message:
Receiver fast PLL <lvds_rx PLL name> and transmitter fast PLL <lvds_tx
PLL name> are merged together
The Quartus II software provides the following message when it cannot
merge the fast PLLs for the LVDS transmitter and receiver pair in the
design:
Can't merge transmitter-only fast PLL <lvds_tx PLL name> and receiver-
only fast PLL <lvds_rx PLL name>
rx_outclock Resource
You can use either the global or regional clock for the rx_outclock
signal. If you select Auto in the Quartus II software, the tool uses any
available lines.
5–64
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005