EP1S40F780C7 Datasheet, PDF (494/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Differential I/O Interface & Fast PLLs
Counter Circuitry
The multiplied clocks bypass the counter taps k and v to directly feed the
SERDES serial registers. These two taps also feed to the quadrant local
clock network and the dedicated RXLOADENA or TXLOADENA pins, as
shown in Figure 5–15. Both k and v are utilized simultaneously during the
data-realignment procedure. When the design does not use the data
realignment, both TXLOADEN and RXLOADEN pins use a single counter.
Figure 5–15. Fast PLL Connection to Logic Array
Counter Circuitry
Post-Scale
Counters
Clock
Distribution
Circuitry
VCO Phase Selection
÷k
Selectable at each PLL
Output Port
8
PLL Output
÷v
÷l
CLK1 SERDES
Circuitry
×1 CLK1 to logic array
or local clocks
TXLOADEN
RXLOADEN
×1 CLK2 to logic array
or local clocks
CLK2 SERDES
Circuitry
Regional clock
clkin
The Stratix device fast PLL has another GCLK connection for general-
purpose applications. The third tap l feeds the quadrant local clock as
well as the global clock network. You can use the l counter's multiplexer
for applications requiring the device to connect the incoming clock
directly to the local or global clocks. You can program the multiplexer to
connect the RXCLKIN signal directly to the local or global clock lines.
Figure 5–15 shows the connection between the incoming clock, the l tap,
and the local or global clock lines.
The differential clock selection is made per differential bank. Since the
length of the clock tree limits the performance, each fast PLL should drive
only one differential bank.
5–22
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005