HC311 Datasheet, PDF (25/26 Pages) Altera Corporation – HardCopy III Device

Chapter 1: DC and Switching Characteristics of HardCopy III Devices
1–23
Glossary
Table 1–33. Glossary Table
Letter
S
Subject
SW (sampling
window)
Definitions
The period of time during which the data must be valid in order to capture it correctly. The
setup and hold times determine the ideal strobe position within the sampling window.
Figure 1–5. Timing Diagram
Bit Time
Single-ended
Voltage
Referenced I/O
Standard
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input
signal values. The AC values indicate the voltage levels at which the receiver must meet its
timing specifications. The DC values indicate the voltage levels at which the final logic state
of the receiver is unambiguously defined. Once the receiver input has crossed the AC value,
the receiver is changed to the new logic state.
The new logic state is maintained as long as the input stays beyond the DC threshold. This
approach is intended to provide predictable receiver timing in the presence of input
waveform ringing.
Figure 1–6. Single-Ended Voltage Referenced I/O Standard
V_CCIO
VOH
V_REF
VIH (AC )
VIH(DC)
VIL (D C)
VIL (AC )
VOL
V_SS
T
t_C
High-speed receiver and transmitter input and output clock period.
TCCS
(channel-to-
The timing difference between the fastest and the slowest output edges, including t_CO
variation and clock skew, across channels driven by the same PLL. The clock is included in
channel-skew) the TCCS measurement (refer to Figure 1–5 under S in this table).
t_DUTY
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
t_{FA LL}
t_INCCJ
t_{OUTPJ_IO}
t_{OUTPJ_DC}
t_RISE
U
—
The timing budget allowed for skew, propagation delays, and data sampling window. (TUI =
1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w)
Signal high-to-low transition time (80-20%)
Cycle-to-cycle jitter tolerance on PLL clock input
Period jitter on general purpose I/O driven by a PLL
Period jitter on dedicated clock output driven by a PLL
Signal low-to-high transition time (20–80%)
—
© December 2008 Altera Corporation
HardCopy III Device Handbook, Volume 3