HC311 Datasheet, PDF (21/26 Pages) Altera Corporation – HardCopy III Device

Chapter 1: DC and Switching Characteristics of HardCopy III Devices
1–19
Switching Characteristics
External Memory I/O Timing Specifications
Table 1–27 and Table 1–28 list HardCopy III device timing uncertainties on the read
and write data paths. Use these specifications to determine timing margins for source
synchronous paths between the HardCopy III FPGA and the external memory device.
Refer to Figure 1–5 in the “SW (sampling window)” row in Table 1–33.
Table 1–27. Sampling Window (SW), Read Side – Preliminary (Note 1)
Sampling Window (ps)
Location (2)
Memory Type
Setup
Hold
VIO
DDR3
TBD
TBD
VIO
DDR2
TBD
TBD
VIO
DDR1
TBD
TBD
VIO
QDRII / II +
TBD
TBD
VIO
RLDRAM II
TBD
TBD
HIO
DDR3
TBD
TBD
HIO
DDR2
TBD
TBD
HIO
DDR1
TBD
TBD
HIO
QDRII / II +
TBD
TBD
HIO
RLDRAM
TBD
TBD
Notes to Table 1–27:
(1) Pending silicon characterization.
(2) VIO (vertical I/O) refers to I/Os in the top and bottom banks; HIO (horizontal I/O) refers to I/Os in the left and right
banks.
Table 1–28. Transmitter Channel-to-Channel Skew (TCCS), Write Side – Preliminary (Note 1)
TCCS (ps)
Location (2)
Memory Type
Lead
Lag
VIO
DDR3
TBD
TBD
VIO
DDR2
TBD
TBD
VIO
DDR1
TBD
TBD
VIO
QDRII / II +
TBD
TBD
VIO
RLDRAM II
TBD
TBD
HIO
DDR3
TBD
TBD
HIO
DDR2
TBD
TBD
HIO
DDR1
TBD
TBD
HIO
QDRII / II +
TBD
TBD
HIO
RLDRAM II
TBD
TBD
Notes to Table 1–28:
(1) Pending silicon characterization.
(2) VIO (vertical I/O) refers to I/Os in the top and bottom banks; HIO (horizontal I/O) refers to I/Os in the left and right
banks.
© December 2008 Altera Corporation
HardCopy III Device Handbook, Volume 3