HC311 Datasheet, PDF (19/26 Pages) Altera Corporation – HardCopy III Device

Chapter 1: DC and Switching Characteristics of HardCopy III Devices
1–17
Switching Characteristics
High-Speed I/O Specifications
Refer to Table 1–33 for definitions of high-speed timing specifications.
Table 1–23 shows the high-speed I/O timing for HardCopy III devices.
Table 1–23. High Speed I/O Specifications – Preliminary (Note 1), (2), (3)
Symbol
Conditions
Clock boost factor W = 2 to 32 (4)
f_HSCLK (input clock frequency) Clock boost factor W = 1 (SERDES bypassed)
Clock boost factor W = 1 (SERDES used)
Dedicate LVDS-f_HSDR (data
rate)
SERDES factor J = 3 to 10
SERDES factor J = 2, uses DDR registers
SERDES factor J = 1, uses SDR register
Dedicated LVDS-f_HSDRDPA (data
—
rate)
LVDS_E_3R-f_HSDR
—
LVDS_E_1R-f_HSDR (data rate)
—
Transmitter
t_X jitter
Total jitter for data rate, 600 Mbps - 1.25 Gbps
Total jitter for data rate, < 600 Mbps
Dedicated LVDS Output t_RISE
and t_FALL
t_DUTY
TCCS
All differential I/O standards
TX output clock duty cycle
All differential I/O standards
Min Typ
Max
Unit
5
—
625
MHz
5
—
600
MHz
150 —
717
MHz
150 —
1250 Mbps
— — TBD (5) Mbps
— — TBD (5) Mbps
150 —
1250 Mbps
——
——
340
Mbps
200
Mbps
——
160
ps
——
0.1
UI
——
200
ps
45 50
55
%
——
100
ps
DPA mode
DPA run length
—
——
(5)
UI
Soft CDR mode
Soft CDR jitter tolerance
Soft CDR run length
Soft-CDR PPM tolerance
—
——
(5)
ps
—
——
(5)
UI
—
——
(5)
PPM
Non DPA mode
Sampling window
All differential I/O standards
——
(5)
ps
Notes to Table 1–23:
(1) When J = 3 to 10, the serializer/deserializer (SERDES) block is used.
(2) When J = 1 or 2, the SERDES block is bypassed.
(3) The minimum specification is dependent on the clock source (PLL and clock pin, for example) and the clock routing resource (global, regional,
or local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate.
(4) The input clock frequency and the W factor must satisfy the following Left and Right PLL output frequency specification: 150 MHz input clock
frequency × W ≤ 1250 MHz.
(5) Pending silicon characterization.
© December 2008 Altera Corporation
HardCopy III Device Handbook, Volume 3