HC311 Datasheet, PDF (23/26 Pages) Altera Corporation – HardCopy III Device

Chapter 1: DC and Switching Characteristics of HardCopy III Devices
1–21
I/O Timing Model
Duty Cycle Distortion (DCD) Specifications
Table 1–32 lists the worst case DCD for HardCopy III devices. Detailed information on
duty cycle distortion are published after characterization.
Table 1–32. Duty Cycle Distortion on HardCopy III I/O Pins – Preliminary (Note 1), (2)
Symbol
Min
Max
Unit
Output Duty Cycle
45
55
%
Notes to Table 1–32:
(1) Preliminary DCD specification applies to clock outputs from PLLs, global clock tree, IOE driving dedicated, and
general purpose I/O pins.
(2) Detailed DCD specifications pending silicon characterization.
I/O Timing Model
The I/O timing specifications for HardCopy III devices will be available in a future
revision of the DC and Switching Characteristics chapter in volume 3 of the HardCopy III
Device Handbook.
Glossary
Table 1–33 shows the glossary for this chapter.
Table 1–33. Glossary Table
Letter
A
B
C
D
Subject
—
—
—
Differential I/O
Standards
Definitions
—
—
—
Figure 1–2. Receiver Input Waveforms
Single-Ended Waveform
Single-Ended Waveform
V_CM
V_CM
Differential Waveform
V_ID
V_OD
Positive Channel (p) = V_IH
Negative Channel (n) = V_IL
Positive Channel (p) = V_OH
Ground
Negative Channel (n) = V_OL
Ground
V_ID
Differential Waveform
p−n=0V
V_ID
V_OD
Transmitter Output Waveform^{p −}s^{n = 0 V}
V_OD
E
—
F
f_HSCLK
f_HSDR
f_HSDRDPA
G
—
H
—
—
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (f_HSDR = 1/TUI),
non-DPA.
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (f_HSDRDPA = 1/TUI), DPA.
—
—
© December 2008 Altera Corporation
HardCopy III Device Handbook, Volume 3