HC311 Datasheet, PDF (24/26 Pages) Altera Corporation – HardCopy III Device

1–22
Chapter 1: DC and Switching Characteristics of HardCopy III Devices
Glossary
Table 1–33. Glossary Table
Letter
I
J
Subject
—
J
JTAG Timing
Specifications
Definitions
—
HIGH-SPEED I/O Block: Deserialization factor (width of parallel data bus).
Figure 1–3. JTAG Timing Specifications
TMS
K
—
L
—
M
—
N
—
O
—
P PLL
Specifications
Q
—
R
RL
TDI
TCK
t_JCH
t_JCP
t_JCL
t_JPSU
t_JPH
TDO
t_JPZX
t_JPCO
t_JPXZ
—
—
—
—
—
The block diagram shown in the following figure highlights the PLL Specification parameters:
Figure 1–4. Diagram of PLL Specifications (Note 1)
CLK
Core Clock
Switchover
fIN
fINPFD
N
PFD
CP
LF
VCO fVCO
CLKOUT Pins
fOUT_EXT
Counters
C0..C9
fOUT
GCLK
RCLK
Key
Reconfigurable in User Mode
M
External Feedback
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
—
Receiver differential input discrete resistor (external to HardCopy III device).
HardCopy III Device Handbook, Volume 3
© December 2008 Altera Corporation