HC311 Datasheet, PDF (18/26 Pages) Altera Corporation – HardCopy III Device

1–16
Chapter 1: DC and Switching Characteristics of HardCopy III Devices
Switching Characteristics
Table 1–21. HardCopy III TriMatrix Memory Block Performance Specifications – Preliminary (Part 2 of 2) (Note 1)
Memory
Block Type
Mode
TriMatrix
Memory Max Unit
True dual-port 16K × 9 or 8K × 18, dual clock
1
300 MHz
True dual-port 4K × 36 dual clock
1
430 MHz
Simple dual-port 16K × 9 or 8K × 18, dual clock
1
300 MHz
Simple dual-port 4K × 36 or 2K × 72, dual clock
1
470 MHz
ROM 1 Port
1
500 MHz
ROM 2 Port
1
450 MHz
M144K
Single-port 16K × 9 or 8K × 18
Single-port 4K × 36
1
330 MHz
1
500 MHz
True dual-port 16K × 9, 8K × 18, or 4K × 36, dual clock with the
read-during-write option set to “Old Data”
1
270 MHz
Simple dual-port 16K × 9, 8K × 18, 4K × 36, or 2K × 72, dual clock with the
1
read-during-write option set to “Old Data”
292 MHz
Simple dual-port 2K × 64 dual clock (with ECC)
1
210 MHz
Min Pulse Width (Clock High Time)
—
1000 ps
Note to Table 1–21:
(1) Pending silicon characterization.
JTAG Specifications
Table 1–22 shows the JTAG timing parameters and values for HardCopy III devices.
Refer to Figure 1–3 in the “HIGH-SPEED I/O Block” row in Table 1–33 for JTAG
timing requirements.
Table 1–22. HardCopy III JTAG Timing Parameters and Values – Preliminary
Symbol
Parameter
Min Max
Unit
t_{JC P}
tJC H
tJC L
tJPSU (TDI)
tJPSU (TMS)
tJP H
tJP CO
tJP Z X
tJP XZ
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time for TDI
JTAG port setup time for TMS
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
30
—
ns
14
—
ns
14
—
ns
1
—
ns
3
—
ns
5
—
ns
—
11
ns
—
14
ns
—
14
ns
Periphery Performance
This section describes the periphery performance, including high-speed I/O, external
memory interface, and OCT calibration block specifications.
HardCopy III Device Handbook, Volume 3
© December 2008 Altera Corporation