HC311 Datasheet, PDF (15/26 Pages) Altera Corporation – HardCopy III Device

Chapter 1: DC and Switching Characteristics of HardCopy III Devices
1–13
Switching Characteristics
PLL Specifications
Table 1–19 describes the HardCopy III PLL specifications when operating in both the
commercial junction temperature range (0° to 85° C) and the industrial junction
temperature range (–40° to 100°C). Refer to Figure 1–4 in the “PLL Specifications” row
in Table 1–33 for a PLL block diagram.
Table 1–19. HardCopy III PLL Specifications – Preliminary (Part 1 of 2) (Note 1)
Symbol
Parameter
Min
f_IN
Input clock frequency
5
fINPF D
Input frequency to the PFD
5
fVC O
PLL VCO operating range
600
tEINDUTY
Input clock or external feedback clock input duty cycle
40
fOUT
Output frequency for internal global or regional clock
—
fOUT_EXT
Output frequency for external clock output
—
tOUTDUTY
Duty cycle for external clock output (when set to 50%)
45
tFC O MP
External feedback clock compensation time
—
tCONF IGPLL
Time required to reconfigure PLL scan chain
—
tCONFIGPHASE Time required to reconfigure phase shift
—
fSC AN C L K
scanclk frequency
—
tLOCK
Time required to lock from end of device power up (4)
—
tDLOCK
Time required to lock dynamically (after switchover or
—
reconfiguring any non-post-scale counters/delays)
f_{CL B W}
PLL closed-loop low bandwidth
—
PLL closed-loop medium bandwidth
—
PLL closed-loop high bandwidth (5)
—
tPL L _ P SE R R
Accuracy of PLL phase shift
—
tAR E S E T
Minimum pulse width on areset signal
10
tINCCJ (4) Input clock cycle to cycle jitter (F_REF ≥ 100 MHz)
—
Input clock cycle to cycle jitter (F_REF < 100 MHz)
—
t (6) OUTPJ_DC Period jitter for dedicated clock output (F_OUT ≥ 100 MHz)
—
Period jitter for dedicate clock output (F_OUT < 100 MHz)
—
t (6) OUTCCJ_DC Cycle to cycle jitter for dedicated clock output (F_OUT ≥ 100 MHz)
—
Cycle to cycle jitter for dedicated clock output (F_OUT < 100 MHz)
—
t (6) OUTPJ_IO Period jitter for clock output on regular I/O (F_OUT ≥ 100 MHz)
—
Period jitter for clock output on regular I/O (F_OUT < 100 MHz)
—
t (6) OUTCCJ_IO Cycle to cycle jitter for clock output on regular I/O (F_OUT ≥
—
100 MHz)
Cycle to cycle jitter for clock output on regular I/O (F_OUT <
—
100 MHz)
Typ Max
Unit
— 717 (2)
MHz
— 325
MHz
— 1300
MHz
— 60
%
— 717 (3)
MHz
— 717 (3)
MHz
50 55
%
— 10
ns
— — scanclk cycles
— — scanclk cycles
— 100
MHz
——
ms
——
ms
——
——
——
——
——
——
——
——
——
——
——
——
——
——
MHz
MHz
MHz
ps
ns
UI (p–p)
ps (p–p)
ps (p–p)
mUI (p–p)
ps (p–p)
mUI (p–p)
ps (p–p)
mUI (p–p)
ps (p–p)
——
mUI (p–p)
© December 2008 Altera Corporation
HardCopy III Device Handbook, Volume 3