HC311 Datasheet, PDF (16/26 Pages) Altera Corporation – HardCopy III Device

1–14
Chapter 1: DC and Switching Characteristics of HardCopy III Devices
Switching Characteristics
Table 1–19. HardCopy III PLL Specifications – Preliminary (Part 2 of 2) (Note 1)
Symbol
Parameter
Min Typ Max
Unit
fDRIFT
Frequency drift after PFDENA is disabled for duration of 100 ms — — —
%
Notes to Table 1–19:
(1) Pending silicon characterization.
(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(3) This specification is limited by the lower of the two: I/O f_MAX or f_OUT of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less
than 200 ps.
(5) High bandwidth PLL settings are not supported in external feedback mode.
(6) Peak-to-peak jitter with a probability level of 10^–12(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to
the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
DSP Block Specifications
Table 1–20 describes the HardCopy III DSP performance specifications.
Table 1–20. HardCopy III DSP Block Performance Specifications – Preliminary (Note 1), (2)
Mode
Number of Multipliers Max Unit
9 × 9-bit multiplier (a, c, e, g) (3)
1
365 MHz
9 × 9-bit multiplier (b, d, f, h) (3)
1
410 MHz
12 × 12-bit multiplier (a, e) (4)
1
365 MHz
12 × 12-bit multiplier (b, d, f, h) (4)
1
410 MHz
18 × 18-bit multiplier
1
495 MHz
36 × 36-bit multiplier
1
365 MHz
Double mode
1
365 MHz
18 × 18-bit multiply adder
2
405 MHz
18 × 18-bit multiply adder
4
405 MHz
18 × 18-bit multiply adder with loop back (5)
2
405 MHz
18 × 18-bit multiply accumulator
4
390 MHz
18 × 18-bit multiply adder with chainout
4
390 MHz
Input Cascade Independent output of 4 18 × 18 bit multiplier
4
455 MHz
36-bit shift (32 bit data)
1
390 MHz
Notes to Table 1–20:
(1) Maximum is for fully pipelined block with round and saturation disabled.
(2) Pending silicon characterization.
(3) The DSP block implements eight independent 9 × 9-bit multipliers using a, b, c, and d for the top half of the DSP
block and e, f, g, and h for the bottom DSP half block multipliers.
(4) The DSP block implements six independent 12 × 12-bit multipliers using a, b, and d for the top half of the DSP half
block and e, f, and h for the bottom DSP half block multipliers.
(5) Maximum for non-pipelined block with loopback input registers disabled with round and saturation disabled.
HardCopy III Device Handbook, Volume 3
© December 2008 Altera Corporation