HC311 Datasheet, PDF (22/26 Pages) Altera Corporation – HardCopy III Device

1–20
Chapter 1: DC and Switching Characteristics of HardCopy III Devices
Switching Characteristics
DLL and DQS Logic Block Specifications
Table 1–29 describes the delay-locked loop (DLL) frequency range specifications for
HardCopy III devices.
Table 1–29. HardCopy III DLL Frequency Range Specifications – Preliminary (Note 1)
Frequency Mode
0
1
2
3
4
5
6
Note to Table 1–29:
(1) Pending silicon characterization.
Frequency Range (MHz)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Resolution (Degrees)
22.5
30
36
45
30
36
45
Table 1–30 describes the DQS phase offset delay per setting for HardCopy III devices.
Table 1–30. Average DQS Phase Offset Delay per Setting – Preliminary (Note 1), (2), (3), (4)
Min
Typ
Max
Unit
7
11
15
ps
Notes to Table 1–30:
(1) The valid settings for phase offset are –64 to +63 for frequency modes 0 to 3 and –32 to +31 for frequency modes
4 to 6.
(2) The typical value equals the average of the minimum and maximum values.
(3) The delay settings are linear with a cumulative delay variation of ±20ps for all speed grades.
(4) Pending silicon characterization.
OCT Calibration Block Specifications
Table 1–31 shows the on-chip termination calibration block specifications for
HardCopy III devices.
Table 1–31. On-Chip Termination Calibration Block Specification – Preliminary
Symbol
OCTUSRCLK
tO CT C AL
t_{O CT S H I FT}
t_{RS_RT}
Description
Min
Clock required by OCT calibration blocks
—
Number of OCTUSRCLK clock cycles required for OCT RS and —
RT calibration
Number of OCTUSRCLK clock cycles required for OCT code to —
shift out per OCT calibration block
Time required to dynamically switch from R_S to R_T
—
Typical
—
1000
Max Unit
20 MHz
— cycles
28
— cycles
2.5
— ns
HardCopy III Device Handbook, Volume 3
© December 2008 Altera Corporation