AK8411 Datasheet, PDF (8/25 Pages) Asahi Kasei Microsystems – Single Channel Input, 16 Bit 5 MSPS Video ADC

ASAHI KASEI
[AK8411]
CISIN
MCLK
TSMP
Data Level Sampling
R3B4~B3=
00b
SHD
(Internal)
01b
10b
11b
R0B3~B2=
00b
Feed through Level Sampling
01b
SHR
(Internal)
10b
11b
D1
D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13
D0
D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12
Fig. 7 Sampling Timing and ADC Output
( in Double Edge, MCLK Sync Sampling Mode )
In Double Edge Mode operation, it is required that a single rising edge of MCLK occurs
during TSMP High duration. When rising edge of MCLK during TSMP High duration occurs
twice and more, proper operation is not made.
SHR pulse width in Double Edge Mode is equal to a half of MCLK period. Falling edge
position of SHR is pre-settable in 1/2 MCLK-period resolution in the range from a single
MCLK clock delay to 2.5 clock delay, counting from the next MCLK rising edge after the
rising edge of MCLK where TSMP = High condition is detected.
MS0457-E-00
8
2006/05