AK8411 Datasheet, PDF (18/25 Pages) Asahi Kasei Microsystems – Single Channel Input, 16 Bit 5 MSPS Video ADC

ASAHI KASEI
[AK8411]
Serial Interface
Clock Input pin SDCLK and Data Input pin SDATA for Serial Interface are shared with A/D
Data Output pins, D0 and D1 respectively. When SDENB becomes low, D0 and D1 are put
into High-Z conditions and it is enabled to input SDCLK and SDATA. SDATA is captured at
the rising edge of SDCLK. SDATA is 16 Bit long. Write “zeros“ from the 1^st Bit to the 5^th Bit.
6^th~8^th Bits are assigned for Register Address where the 6^th Bit is MSB and the 8^th Bit is LSB.
9^th~ 16^th Bits are assigned for Data where the 9^th Bit is MSB and the 16^th Bit is LSB.
16 and more rising edges of SDCLK are required while SDENB is low, from the time to fall
to the time to rise. When it is less than 16 rises, registers will not be written properly.
If it is more than 16 rises while SDENB is low, from falling to rising, the last 16 edges
become effective. There is a possibility that an erroneous data will be written into registers if
noises occur on D0 Output / SDCLK input pin and D1 Output / SDATA input pin when these
pins are at High-Z conditions. To avoid this, resistors should be connected between D0 /
SDCLK pin, D1 / SDATA pin and AVSS respectively to pull-down these pins.
SDENB
D0
SDCLK
D1
SDATA
High-Z
High-Z
0 0 0 0 0 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
High-Z
High-Z
Fig. 22 Register Write Operation
00
Control Registers
It takes 10 ms maximum from register contents to be modified till valid data to be output on
D0 & D1 pins. When to modify register contents when R0 B7 is set to “zero” (Reset condition),
set R0 B7 to “one“ (release from Reset) first, then modify other registers, including B6 ~B0
Bits at Address Zero. Un-used bits can be written with either “zeros” or “ones”.
Address Init.
B7
B6
B5
B4
B3
B2
B1
B0
0
00h Reset 0 Output Input Reference level Clock Power
buffer mode sampling position mode down
drivability
1
80h
Offset DAC Data ( 8bit )
2
00h
Un-used
PGA Gain data (6bit)
3
00h
Un-used
SHD
SHD width
0
0
Output
mode
order
4
00h
for testing purpose
5
00h
for testing purpose
MS0457-E-00
18
2006/05