AK8411 Datasheet, PDF (20/25 Pages) Asahi Kasei Microsystems – Single Channel Input, 16 Bit 5 MSPS Video ADC

ASAHI KASEI
[AK8411]
„ R0 B1
Clock Mode
B1
Clock mode
0 Single edge ( at reset )
1 Double edge
In Single Edge Mode operation, D0 & D1 data of ADC are output in sync with rising edge of
MCLK. Required MCLK frequency is 8 x Pixel rate. In Double Edge Mode operation, data
are output in sync with both rising and falling edges of MCLK. Required MCLK frequency is
4 x Pixel rate.
„ R0 B0
Operation mode select
B0
Operation mode
0 Power down ( at reset )
1 Normal operation
When this bit is set to ”0“, logic circuit excluding Serial Interface stops its operation while
analog part is powered-down. Register contents just before being put into power-down
operation are retained even during Power-Down operation.
„ R1 Offset DAC setting
B7∼B0
00000000
:
01111111
10000000
10000001
:
11111111
Offset level
−240mV
:
−1.88mV
(at reset )
0mV
+1.88mV
:
+238mV
Offset(x) = −240 + 480 / 256 × x[mV] (x=0~255) where x is a register set value.
at reset : x=128, Offset(128)=0mV
offset DAC setting
FFh
max.
80h
00h
min.
Black
S/H
correction
PGA
ADC
CIS signal
S/H output level after Black correction
output code
Fig. 23 Level Changes by Offset Setting
(in DC Direct-Coupled Mode operation = Positive polarity operation)
MS0457-E-00
20
2006/05