AK8411 Datasheet, PDF (2/25 Pages) Asahi Kasei Microsystems – Single Channel Input, 16 Bit 5 MSPS Video ADC

ASAHI KASEI
CISIN
Circuit Block Description
VCLP VCOM VRP VRN
DC Connect Mode
CDS Mode
Clamp Switch
CDS
S/H
Reference Voltage
PGA
16bit ¹⁶ Output
ADC
Control
8bit DAC
6
8
Control
Registers
[AK8411]
TESTO
RESETB
D0/SDCLK
D1/SDATA
SDENB
TSMP MCLK AVDD AVSS DRVDD DRVSS
Fig. 1 Block Diagram
„ Sensor Interface Part
Circuit to sample & hold input signal which is fed on CISIN pin. Signal input range is 1.98V
(typ.). There are two input modes, DC Direct Coupled Mode and CDS Mode. In DC Direct
Coupled Mode, Positive polarity signal is handled. In CDS Mode, Negative polarity signal is
handled. Signal Reference Voltage should be input on VCLP pin in DC Direct Coupled mode.
In CDS mode, Voltage level to clamp signal is internally generated and it is output on VCLP
pin.
„ Black Level Correction Circuit
Circuit to add an Offset voltage to the sampled signal level. Voltage range of DAC which
generates Offset is ±240 mV (typ.) and its resolution is 8 Bit.
„ PGA Part
Circuit to adjust signal amplitude, prior to AD conversion. Adjustable gain range is from 0dB
to 13.9dB ( typ. ) (1.0× ~ 4.9×) and its resolution is 6 Bit.
„ ADC Part
AD conversion circuit to convert into Digital data an Analog signal after both Black level
correction and Gain adjustment are made. Its resolution is 16 Bit with its maximum
conversion rate of 5MSPS. Data output is in a straight Binary code. 0000h is output at Black
level input ( 0Vpp input ) and FFFFh is output at White level input ( maximum input ).
„ Output Control Part
A 16 Bit-wide ADC output data is re-arranged into 2 Bit ×8 cycle stream at this part. In
Single Edge Mode operation, Data is output at the rising edge of MCLK. In Double Edge
Mode operation, it is output at both rising and falling edges of MCLK.
„ Reference Voltage Generator
Circuit to generate internal reference voltages. Clamp Reference Voltage VCLP, internal
MS0457-E-00
2
2006/05