AK8411 Datasheet, PDF (3/25 Pages) Asahi Kasei Microsystems – Single Channel Input, 16 Bit 5 MSPS Video ADC

ASAHI KASEI
[AK8411]
common voltage VCOM and ADC reference voltages VRP and VRN are generated. Each
reference voltage is output on respective device pins. For voltage stabilization, capacitors
should be connected between respective pins and AVSS.
„ Serial Interface Part
A 3-Wire Interface circuit to access setting-registers. SDCLK (clock) and SDATA (data) pins
are shared with D0 and D1 pins of ADC Data Output. When SDENB pin is at low, D0 and
D1pins function as SDCLK and SDATA input pins. In order to avoid both SDCLK and
SDATA pins to become floating condition, proper pull-down resistors should be connected
between D0 / SDCLK pin, D1 / SDATA pin and AVSS respectively.
Pin Functions
No.
Name
1
TSMP
2
MCLK
3
RESETB
4
D1/SDATA
5
DRVDD
6
DRVSS
7
D0/SDCLK
8
SDENB
9
VCOM
10 VRN
11 VRP
12 VCLP
13 CISIN
14 AVSS
15 AVDD
16 TESTO
IO
I
I
I
O
I
PWR
PWR
O
I
I
O
O
O
I
O
I
PWR
PWR
O
Description
Sampling Timing
Main Clock
Single edge mode : 8 × Sampling frequency
Double edge mode : 4 × Sampling frequency
Reset pin : Active Low, on chip pull-up resister : 100kΩ (typ.)
SDENB=High ; A/D Data output : Upper Bit
SDENB=Low ; Serial Interface Data input
A/D Output buffer power supply
A/D Output buffer ground
SDENB=High ; A/D Data output : Lower Bit
SDENB=Low ; Serial Interface Clock input
Serial Interface Enable
Internal Reference Voltage
ADC Negative Reference Voltage
ADC Positive Reference Voltage
Sensor Reference Level input at DC Direct Coupled mode
Clamp Level output at CDS mode
Sensor Signal input
Analog ground
Analog power supply
Test Output pin. Should be left open
I: Input , O: Output , PWR: Power Supply
Pin Allocation
TSMP
MCLK
RESETB
D1/SDATA
DRVDD
DRVSS
D0/SDCLK
SDENB
1
16
2
15
3
14
4 _{Top View} 13
5
12
6
11
7
10
8
9
TESTO
AVDD
AVSS
CISIN
VCLP
VRP
VRN
VCOM
MS0457-E-00
Fig. 2 Pin Allocation
3
2006/05