AK8411 Datasheet, PDF (19/25 Pages) Asahi Kasei Microsystems – Single Channel Input, 16 Bit 5 MSPS Video ADC

ASAHI KASEI
[AK8411]
„ R0 B7
Register reset
B7
Operation
0 Reset ( at reset )
1 release from Reset
When this bit is set to “0“, all other registers are set to initial values, except for this bit.
When this bit is “0“, write operation into all other registers except for this bit is ignored.
„ R0 B6
Reserved
write “ 0 “.
„ R0 B5
Output Buffer Drivability
B5
Output mode
0 Normal ( at reset )
1 2× ( Double )
When Output Buffer Drivability is set to “2ד, maximum output current of the output buffers
increases. This selection is used when the Data Output Delay which is referenced to Data
Capture clock becomes too large, due to capacitive loading.
„ R0 B4
Input mode
B4
Input mode
0 DC Direct-Coupled mode ( at Reset )
1 CDS mode
Signal Polarity which can be processed by the AK8411 is determined by the type of Input
Modes. In DC Direct-Coupled Mode, it handles Positive polarity (signal is output toward
higher voltage than reference level) and in CDS Mode, it handles Negative polarity (signal is
output toward lower voltage than reference level).
„ R0 B3~B2 Feed-Through Level Sampling Pulse (SHR) Position
B3 B2
SHR Position
at Single edge mode
SHR Position
at Double edge mode
0 0 2×MCLK delay ( at reset ) from the 1×MCLK delay ( at reset ) from the
Data Level Sampling position
Data Level Sampling position
0 1 3×MCLK delay
1.5×MCLK delay
1 0 4×MCLK delay
2×MCLK delay
1 1 5×MCLK delay
2.5×MCLK delay
This register is to set fall position of internal pulse SHR, at which feed-through level is
sampled. Pulse width of SHR is fixed. SHR is enabled only when the device is in CDS Mode
operation. SHR stops while it is in DC Direct-Coupled Mode operation.
MS0457-E-00
19
2006/05