AK8411 Datasheet, PDF (12/25 Pages) Asahi Kasei Microsystems – Single Channel Input, 16 Bit 5 MSPS Video ADC

ASAHI KASEI
(Note 6) Relative value to the gain at PGA setting is 00h.
(Note 7) A full-scale minus 2 dB, 1 MHz sine-wave signal is input.
(Note 8) A clock supply to MCLK is stopped.
(Note 9) At the capacitive load is 20pF.
[AK8411]
„ Switching Characteristics
(AVDD=3.135~3.465V, DRVDD=3.0~3.6V, Ta=0∼70°C, unless otherwise specified)
#.
Item
Pin Min. Typ. max Unit Conditions
.
1 MCLK cycle time (T)
MCLK
25
125 ns Single edge
50
250 ns Double edge
2 MCLK ‘H’ , ’L’ width
MCLK
10
ns Single edge
25
ns Double edge
3 TSMP set-up time
TSMP
5
ns (Note 1)
(referenced to MCLK↑)
4 TSMP hold time
TSMP
5
ns (Note 1)
(referenced from MCLK↑)
5 Aperture delay
CISIN
2
ns Data level
(referenced from MCLK↑)
6 Aperture delay
CISIN
2
ns Reference level
(referenced from MCLK↑)
7 TSMP period
TSMP
8T
Single edge
(MCLK period-unit )
4T
Double edge
8 Data output delay
D0, D1
2
25 ns Single edge
(referenced from MCLK↑)
At load:20pF,
(Note 2)
2
20 ns Single edge
At load:20pF,
(Note 3)
Data output delay
D0, D1
2
25 ns Double edge
(referenced from MCLK↑↓)
At load :20pF,
(Note 2)
2
20 ns Double edge
At load :20pF,
(Note 3)
9 Pipeline delay
D0, D1
4
TSMP
period-unit
10 Reset pulse width
RESETB 50
ns
(Note 1) Number of MCLK rising edges during TSMP = H duration is allowed to be 1 to 3
times in Single Edge Mode operation, and only a single edge is allowed in Double
Edge mode operation.
(Note 2) when output buffer drivability is set at normal setting
(Note 3) when output buffer drivability is set at 2× setting
MS0457-E-00
12
2006/05