AK8411 Datasheet, PDF (6/25 Pages) Asahi Kasei Microsystems – Single Channel Input, 16 Bit 5 MSPS Video ADC

ASAHI KASEI
[AK8411]
„ D0, D1
A/D Data output
A/D data is output in 2 Bit wide x 8 cycles. In Single Edge Mode operation, A/D data D0 &
D1 are output in sync with the rising edges of MCLK. In Double Edge Mode operation, D0 &
D1 are output in sync with both rising and falling edges of MCLK.
CISIN
MCLK
TSMP
Data Level Sampling
R3B4~B3=
00b
SHD
(Internal)
01b
10b
11b
R0B3~B2=
00b
Feed through Level Sampling
01b
SHR
(Internal)
10b
11b
D1
D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13
D0
D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12
Fig. 5 Sampling Timing and ADC Output
( in Single Edge, MCLK Sync Sampling Mode )
In Single Edge Mode operation, it is required that 1 ~ 3 rising edges of MCLK occur during
the TSMP High duration time. When MCLK rises twice or more during the TSMP High
duration time, the last MCLK rising edge becomes effective. When rising edges of MCLK
during TSMP High duration time occur 4 times and more, correct operation is not made.
When the Data Level Sampling Mode is MCLK Sync sampling, SHD falls at the next MCLK
rise after the last MCLK rise which detected TSMP = High condition. High duration time of
SHD can be set by register. When the clock mode is in Single Edge Mode, it can be set from
one to four MCLK periods in a single period unit. When the clock mode is in Double Edge
Mode, it can be set from a half to 2 MCLK periods in a half period unit.
In Single Edge Mode operation, pulse width of SHR is equal to a single MCLK period. Falling
edge position of SHR is pre-settable in MCLK-period resolution in the range from 2 clock
MCLK delay to 5 clock MCLK delay , counting from the next MCLK rising edge after the
MS0457-E-00
6
2006/05