AK4495EQ Datasheet, PDF (56/63 Pages) Asahi Kasei Microsystems – Quality-oriented Premium 32-Bit 2ch DAC

Digital Ground
System
Controller
Analog Ground
[AK4495S/95]
34 _AOUTLP
35 VCOML
36 VREFLL
37 VREFLL
38 VREFHL
39 VREFHL
40 AVDD
41 AVSS
42 MCLK
43 DVSS
44 DVDD
AK4495S/95
AOUTRP 22
VCOMR 21
VREFLR 20
VREFLR 19
VREFHR 18
VREFHR 17
ACKS/CAD1 16
DEM1 15
DEM0 14
I2C 13
PSN 12
Figure 37. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDDL/R and
DVDD respectively. AVDD and VDDL/R are supplied from analog supply in system and DVDD is supplied
from digital supply in system. Power lines of AVDD, VDDL/R and DVDD should be distributed separately
from the point with low impedance of regulator etc. The power up sequence between AVDD, VDDL/R and
DVDD is not critical. AVSS, DVSS, VSSL, VSSR must be connected to the same analog ground
plane. Decoupling capacitors for high frequency should be placed as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin
is normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and
VREFLL/R should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the
effects of high frequency noise. No load current may be drawn from VCML/R pin. All signals, especially
clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid unwanted noise
coupling into the AK4495S/95.
3. Analog Outputs
The analog outputs are full differential outputs and 2.8Vpp (typ, VREFHL/R  VREFLL/R = 5V) centered
around VDDR/2 and VDDL/2 voltages. The differential outputs are summed externally, V_AOUT = (AOUT+) 
(AOUT) between AOUT+ and AOUT. If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R
 VREFLL/R = 5V). The bias voltage of the external summing circuit is supplied externally. The input data
format is 2's complement. The output voltage (V_AOUT) is a positive full scale for 7FFFFFH (@24bit) and a
negative full scale for 800000H (@24bit). The ideal V_AOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the
audio passband. Figure 38 shows an example of external LPF circuit summing the differential outputs by an
op-amp. Figure 39 shows an example of differential outputs and LPF circuit example by three op-amps.
MS1560-E-02
- 56 -
2014/04