AK4495EQ Datasheet, PDF (45/63 Pages) Asahi Kasei Microsystems – Quality-oriented Premium 32-Bit 2ch DAC

[AK4495S/95]
(2) I²C-bus Control Mode (I2C pin = “H”)
The AK4495S/95 supports the fast-mode I²C-bus (max: 400kHz, Ver 1.0).
(2)-1. WRITE Operations
Figure 27 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by a START
condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition
(Figure 33). After the START condition, a slave address is sent. This address is 7 bits long followed by the
eighth bit that is a data direction bit (R/W). The most significant five bits of the slave address are fixed as
“00100”. The next bits are CAD1 and CAD0 (device address bits). This bit identifies the specific device on the
bus. The hard-wired input pin (cAD1pins, CAD0 pin) sets these device address bits (Figure 28). If the slave
address matches that of the AK4495S/95, the AK4495S/95 generates an acknowledge and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH)
during the acknowledge clock pulse (Figure 34). A R/W bit value of “1” indicates that the read operation is to
be executed, and “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4495S/95 and the format is MSB first.
(Figure 29). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 30).
The AK4495S/95 generates an acknowledge after each byte is received. Data transfer is always terminated by
a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH
defines a STOP condition (Figure 33).
The AK4495S/95 can perform more than one byte write operation per sequence. After receipt of the third byte
the AK4495S/95 generates an acknowledge and awaits the next data. The master can transmit more than one
byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data
packet the internal address counter is incremented by one, and the next data is automatically taken into the next
address. If the address exceeds 2FH prior to generating a stop condition, the address counter will “roll over” to
00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the
data line can only be changed when the clock signal on the SCL line is LOW (Figure 35) except for the START
and STOP conditions.
SDA
S
T
S
A
R/W= “0”
T
R
O
T
P
S
Slave
Address
Sub
Address(n)
Data(n)
Data(n+1)
Data(n+x) P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 27. Data Transfer Sequence at I²C Bus Mode
0
0
1
0
0 CAD1 CAD0 R/W
Figure 28. The First Byte
(CAD0 is set by the pin)
0
0
0
A4 A3 A2 A1 A0
Figure 29. The Second Byte
D7 D6 D5 D4 D3 D2 D1 D0
Figure 30. The Third Byte and After The Third Byte
MS1560-E-02
- 45 -
2014/04