AK4495EQ Datasheet, PDF (44/63 Pages) Asahi Kasei Microsystems – Quality-oriented Premium 32-Bit 2ch DAC

[AK4495S/95]
■ Register Control Interface
(1) 3-wire Serial Control Mode (I2C pin = “L”)
Pins (parallel control mode) or registers (serial control mode) can control the functions of the AK4495S/95. In
parallel control mode, the register setting is ignored, and in serial control mode the pin settings are ignored.
When the state of the PSN pin is changed, the AK4495S/95 should be reset by the PDN pin. The serial control
interface is enabled by the PSN pin = “L”. Internal registers may be written to through3-wire µP interface pins:
CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits, C1/0), Read/Write (1-bit;
fixed to “1”), Register address (MSB first, 5-bits) and Control data (MSB first, 8-bits). The data is output on a
falling edge of CCLK and the data is received on a rising edge of CCLK. The writing of data is valid when
CSN “”. The clock speed of CCLK is 5MHz (max).
Function
Parallel Control Mode Serial Control Mode
Audio Format
Y
Y
Auto Setting Mode
Y
Y
De-emphasis
Y
Y
SMUTE
Y
Y
DSD Mode
-
Y
EX DF I/F
-
Y
Zero Detection
-
Y
Sharp Roll off filter
Y
Y
Slow Roll off filter
Y
Y
Minimum delay Filter
Y
Y
Digital Attenuator
-
Y
Sound Quality Adjustment
-
Y
Clock Synchronize
-
Y
Table 26. Function List1 (Y: Available, -: Not available)
Setting the PDN pin to “L” resets the registers to their default values. In serial control mode, the internal timing
circuit is reset by the RSTN bit, but the registers are not initialized.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 26. Control I/F Timing
* 3-wire serial control mode does not support read commands.
* When the AK4495S/95 is in power down mode (PDN pin = “L”) or the MCLK is not provided, writing into
control registers is prohibited.
* The control data can not be written when the CCLK rising edge is 15 times or less or 17 times or more during
CSN is “L”.
MS1560-E-02
- 44 -
2014/04