AK4495EQ Datasheet, PDF (31/63 Pages) Asahi Kasei Microsystems – Quality-oriented Premium 32-Bit 2ch DAC

[AK4495S/95]
[2] DSD Mode
The external clocks, which are required to operate the AK4495S/95, are MCLK and DCLK. MCLK should be
synchronized with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
The AK4495S/95 is automatically placed in reset state when MCLK is stopped during a normal operation
(PDN pin =“H”), and the analog output becomes VDDR/2 and VDDL/2 voltages (typ.).
DCKS bit
0
1
MCLK Frequency DCLK Frequency
512fs
64fs
768fs
64fs
Table 15. System Clock (DSD Mode)
(default)
The AK4495S/95 supports DSD data stream of 2.8224MHz (64fs) and 5.6448MHz (128fs). The data sampling
speed is selected by DSDSEL bit. 2.8224MHz (64fs) is supported when DSDSEL bit = “0” and 5.6448MHz
(128fs) is supported when DSDSEL bit = “1”.
DSDSEL bit DSD data stream
0
2.8224MHz (default)
1
5.6448MHz
Table 16. DSD Sampling Speed Control
The AK4495S/95 has a Volume pass function. Three modes are selectable by DSDD1-0 bits.
DSDD1 bit DSDD0 bit
Mode
0
0
Normal path (default)
0
1
Volume pass
1
0
Reserved
1
1
Reserved
Table 17. DSD Play Back Mode Control
The AK4495S/95 has an internal mute function that mutes the output when DSD audio data becomes all “1” or
all “0” for 2048 samples (1/fs). DDM bit controls this function. When the output is muted, L channel and R
channel flags are indicated on DML bit and DMR bit, respectively. DMC bit controls mute release whether
releasing the mute automatically when the signal level returns to a normal level or releasing the mute manually
by a register. DMRE bit releases the mute when manual controlling is selected.
MS1560-E-02
- 31 -
2014/04