AK4495EQ Datasheet, PDF (46/63 Pages) Asahi Kasei Microsystems – Quality-oriented Premium 32-Bit 2ch DAC

[AK4495S/95]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4495S/95. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after the
receipt of the first data word. After receiving each data packet the internal address counter is incremented by
one, and the next data is automatically taken into the next address. If the address exceeds 09H prior to
generating stop condition, the address counter will “roll over” to 00H and the data of 00H will be read out.
The AK4495S/95 supports two basic read operations: CURRENT ADDRESS READ and RANDOM
ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4495S/95 has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address with
R/W bit “1”, the AK4495S/95 generates an acknowledge, transmits 1-byte of data to the address set by the
internal address counter and increments the internal address counter by 1. If the master does not generate an
acknowledge but generates a stop condition instead, the AK4495S/95 ceases the transmission.
SDA
S
T
A
R/W= “1”
R
T
S
Slave
Address
Data(n)
Data(n+1) Data(n+2)
A
A
A
A
C
C
C
C
K
K
K
K
S
T
O
P
Data(n+x) P
A
A
C
C
K
K
Figure 31. Current Address Read
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the
slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The master
issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register
address is acknowledged, the master immediately reissues the start request and the slave address with the R/W
bit “1”. The AK4495S/95 then generates an acknowledge, 1 byte of data and increments the internal address
counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the
AK4495S/95 ceases the transmission.
SDA
S
T
A
R
T
S
Slave
Address
R/W= “0”
Sub
Address(n)
A
C
K
S
T
A
R
T
S
Slave
Address
A
C
K
R/W= “1”
Data(n)
A
C
K
Data(n+1)
A
A
C
C
K
K
S
T
O
P
Data(n+x) P
A
A
C
C
K
K
Figure 32. Random Address Read
MS1560-E-02
- 46 -
2014/04