AK4495EQ Datasheet, PDF (51/63 Pages) Asahi Kasei Microsystems – Quality-oriented Premium 32-Bit 2ch DAC

[AK4495S/95]
Addr Register Name
02H Control 3
Default
D7
D6
DP
0
0
0
SLOW: Slow Roll-off Filter Enable
0: Sharp roll-off filter (default)
1: Slow roll-off filter
D5
DCKS
0
D4
DCKB
0
D3
MONO
0
D2
DZFB
0
D1
SELLR
0
D0
SLOW
0
SD
SLOW
Mode
0
0
Sharp roll-off filter
0
1
Slow roll-off filter
1
0
Short delay sharp roll off filter (default)
1
1
Short delay slow roll off filter
Table 14. Digital Filter Setting
SELLR: The data selection of L channel and R channel, when MONO mode
0: All channels output L channel data, when MONO mode. (default)
1: All channels output R channel data, when MONO mode.
This bit is enabled when MONO bit is “1”. The AK4495S/95 outputs Lch data to both channels
when SELLR bit is “0” and outputs Rch data to both channels when SELLR bit is “1”.
DZFB: Inverting Enable of DZF
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
DZFE DZFB
Data
DZF-pin
0
-
L
0
1
-
H
not zero
L
0
Zero detect
H
1
not zero
H
1
Zero detect
L
Table 23. Zero Detect Function and DZF Pin Output
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
When MONO bit is “1”, MONO mode is enabled.
DCKB:Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP: DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When D/P bit is changed, the AK4495S/95 should be reset by RSTN bit.
MS1560-E-02
- 51 -
2014/04