AK4495EQ Datasheet, PDF (21/63 Pages) Asahi Kasei Microsystems – Quality-oriented Premium 32-Bit 2ch DAC

[AK4495S/95]
Control Interface Timing
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH 80
ns
CDTI Setup Time
tCDS
50
ns
CDTI Hold Time
tCDH
50
ns
CSN High Time
tCSW
150
ns
CSN “” to CCLK “”
tCSS
50
ns
CCLK “” to CSN “”
tCSH
50
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA 0.6
SDA Hold Time from SCL Falling
(Note 20)
tHD:DAT 0
SDA Setup Time from SCL Rising
tSU:DAT 0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO 0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
ns
400 kHz
-
s
-
s
-
s
-
s
-
s
-
s
-
s
0.3 s
0.3 s
-
s
50 ns
Capacitive load on bus
Cb
-
400 pF
Reset Timing
PDN Pulse Width
(Note 21)
tPD
150
ns
Note 17. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4495S/95
should be reset by the PDN pin or RSTN bit.
Note 18. BICK rising edge must not occur at the same time as LRCK edge.
Note 19. DSD data transmitting device must meet this time.
Note 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 21. The AK4495S/95 can be reset by bringing the PDN pin to “L”.
MS1560-E-02
- 21 -
2014/04