AK4613 Datasheet, PDF (48/69 Pages) Asahi Kasei Microsystems – 4/12-Channel Audio CODEC

[AK4613]
■ Reset Function
When RSTN bit= “0”, the analog and digital part of ADC and the digital part of DACs are powered-down, but the internal
register are not initialized. The analog outputs go to VCOM voltage regardless of the DVMPD pin setting, then DZF1-2
pins go to “H” and SDTO1-2 pin goes to “L”. As some click noise occurs, the analog output should be muted externally if
the click noise influences system application. Figure 46 shows the power-up sequence.
RSTN bit
Internal
RSTN bit
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
DZF1/DZF2
Normal Operation
4~5/fs (8)
Power-down
3~4/fs (9)
518/fs ⁽¹⁾
Init Cycle
Normal Operation
Normal Operation
Digital Block Power-down
GD ⁽²⁾
Normal Operation
GD
(3)
“0”data
“0”data
(2)
GD
(6) (5)
(6)
Don’t care
8∼9/fs (7)
(4)
GD
Notes:
(1) The analog section of the ADC is initialized after exiting reset state.
(2) Digital output corresponding to the analog inputs, and analog outputs corresponding to the digital inputs have group
delay (GD).
(3) ADC output is “0” data at power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the click noise
influences system application.
(5) The analog outputs go to VCOM voltage regardless of the DVMPD pin setting when RSTN bit becomes “0”.
(6) Click noise occurs at 4∼5/fs after RSTN bit becomes “0”, and occurs at 3∼4/fs after RSTN bit becomes “1”.
(7) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 8~9/fs after RSTN bit becomes “1”.
(8) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
(9) There is a delay, 3~4/fs from RSTN bit “1” to the start of initial cycle.
Figure 46. Reset sequence example
MS1052-E-02
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2010/03