AK4613 Datasheet, PDF (43/69 Pages) Asahi Kasei Microsystems – 4/12-Channel Audio CODEC

[AK4613]
■ Overflow Detection
The AK4613 has an overflow detect function for the analog input. The overflow detect function is enabled when the
OVFE bit is set to “1”. Overflow detection is applied to the analog input of each channel, and the result is OR’d. OVF1/2
pins goes to “H” according to the group set by OVFM2-0 bits, if analog input of Lch or Rch overflows (more than
-0.3dBFS). When the analog input is overflowed, the output signal of OVF1/2 pins have the same group delay as ADC
(GD = 16/fs = 333μs @fs=48kHz). OVF1/2 pins are “L” for 518/fs (=11.8ms @fs=48kHz) after PDN = “↑”, and then
overflow detection is enabled.
Mode
0
1
2
3
4
5
6
7
OVFM2
0
0
0
0
1
1
1
1
OVFM1
0
0
1
1
0
0
1
1
OVFM0
0
1
0
1
0
1
0
1
LIN1 or RIN1
OVF1
OVF1
-
OVF2
OVF2
LIN2 or RIN2
OVF1
OVF2
OVF1
-
OVF2
disable (OVF2=OVF1= “L”)
(default)
Table 15. Overflow detect control (OVFE bit = “1”)
■ Zero Detection
The AK4613 has two pins for zero detect flag outputs. Zero detect function is enabled when the OVFE bit is set to “0”.
Channel grouping can be selected by the DZFM3-0 bits. (Table 16) The DZF1 pin corresponds to the group 1 channels
and the DZF2 pin corresponds to the group 2 channels. DZF1 is AND operation of all twelve channels and DZF2 is
disabled (“L”) at mode 0. When the input data of all channels in the group 1(group 2) are continuously zeros for 8192
LRCK cycles, the DZF1 (DZF2) pin goes to “H”. The DZF1 (DZF2) pin immediately returns to “L” if input data of any
channels in the group 1(group 2) is not zero.
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DZFM
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
L1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
R1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
L2
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
R2
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
L3
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
AOUT
R3
L4
DZF1 DZF1
DZF1 DZF1
DZF1 DZF1
DZF1 DZF1
DZF1 DZF1
DZF1 DZF1
DZF1 DZF2
DZF2 DZF2
DZF2 DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
R4
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
disable (DZF1=DZF2 = “L”)
L5
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
R5
DZF1
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
L6
DZF1
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
R6
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
(default)
Table 16. Zero detect control (OVFE bit = “0”)
MS1052-E-02
- 43 -
2010/03