AK4613 Datasheet, PDF (27/69 Pages) Asahi Kasei Microsystems – 4/12-Channel Audio CODEC

[AK4613]
OPERATION OVERVIEW
■ System Clock
It is possible to select the clock source either extra clock input or X’tal input for the AK4613. (Figure 17, Figure 18) The
external clocks which are required to operate the AK4613 in slave mode are MCLK, LRCK and BICK. MCLK should be
synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS bit= “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each
sampling speed is set automatically. (Table 3, Table 4, Table 5). In Auto Setting Mode (ACKS bit= “1”), as MCLK
frequency is detected automatically (Table 6) and the internal master clock attains the appropriate frequency (Table 7), so
it is not necessary to set DFS.
In master mode, only MCLK is required. Master Clock Input Frequency should be set with the CKS1-0 bits, and the
sampling speed should be set by the DFS1-0 bits. The frequencies and the duties of the clocks (LRCK, BICK) are not
stabile immediately after setting CKS1-0 bits and DFS1-0 bits up.
After exiting reset at power-up in slave mode, the AK4613 is in power-down mode until MCLK and LRCK are input.
If the clock is stopped, click noise occurs when restarting the clock. Mute the digital output externally if the click noise
influences system applications.
DFS1
0
0
1
1
DFS0
Sampling Speed Mode (fs)
0
Normal Speed Mode
32kHz~48kHz (default)
1
Double Speed Mode
64kHz~96kHz
0
Quad Speed Mode
128kHz~192kHz
1
N/A
-
(N/A: Not available)
Table 1. Sampling Speed (Manual Setting Mode)
CKS1
0
0
1
1
CKS0
0
1
0
1
Normal Speed
Mode
256fs
384fs
512fs
512fs
Double Speed
Mode
256fs
256fs
256fs
256fs
Quad Speed
Mode
128fs
128fs
128fs
128fs
(default)
Table 2. Master Clock Input Frequency Select (Master Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLK (MHz)
384fs
12.2880
16.9344
18.4320
512fs
16.3840
22.5792
24.5760
BICK (MHz)
64fs
2.0480
2.8224
3.0720
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
MS1052-E-02
- 27 -
2010/03