AK4613 Datasheet, PDF (47/69 Pages) Asahi Kasei Microsystems – 4/12-Channel Audio CODEC

[AK4613]
All ADCs and all DACs can be powered-down individually through the PMADC bits and PMDAC bits, when the PMVR
bit “1”. ADC1-2 can be power-down individually through the PMAD2-1 bits. DAC1-6 can be power-down individually
by PMDA6-1 bits. In this case, the internal register values are not initialized. When PMADC bit = “0”, SDTO1-2 goes to
“L”. When PMDAC bit = “0”, the analog outputs go to VCOM voltage when the DVMPD pin is “L”, and the analog
outputs go to Hi-Z when the DVMPD pin “H”. When PMDAC bit = “0”, DZF1-2 pins go to “H”. As some click noise
occurs, the analog output should be muted externally if the click noise influences system applications. Figure 45 shows
the power-down and power-up sequences.
PMVR bit
PMADC/PMDAC bit
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
DZF1/DZF2
4~5/fs (10)
Normal Operation
Power-down
Normal Operation
GD ⁽³⁾
Power-down
(4)
“0”data
“0”data
GD(3)
(7)
(5)
Don’t care
(8)
3~4/fs (11)
518/fs ⁽¹⁾
Init Cycle
516/fs (2)
Init Cycle
Normal Operation
Normal Operation
GD
(6)
GD
(7)
8∼9/fs (12)
External
Mute
(9)
Mute ON
Notes:
(1) The analog section of ADC is initialized after exiting power-down state.
(2) The analog section of DAC is initialized after exiting power-down state.
(3) Digital output corresponding to the analog inputs and analog outputs corresponding to the digital inputs have group
delay (GD).
(4) ADC output is “0” data at power-down state.
(5) The analog outputs are VCOM voltage when the DVMPD pin “L”, and the analog outputs go to Hi-Z when the
DVMPD pin “H” in power-down mode.
(6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise
influences system application.
(7) Click noise occurs at 4∼5/fs after PMDAC bit becomes “0”, and occurs at 519∼520/fs after PMDAC bit becomes
“1”.
(8) DZF1-2 pins are “H” in power-down mode (PMDAC bit = “0”).
(9) Mute the analog output externally if the click noise (7) influences system application.
(10) There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable ADC power-down.
There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable DAC power-down.
(11) There is a delay, 3~4/fs from PMADC and PMDAC bits become “1” to the start of initial cycle.
(12) DZF pin= “L” for 8∼9/fs after PMDAC bit becomes “1”.
Figure 45. Bit power-down/Bit power-up sequence example
MS1052-E-02
- 47 -
2010/03