AK4613 Datasheet, PDF (46/69 Pages) Asahi Kasei Microsystems – 4/12-Channel Audio CODEC

[AK4613]
■ Power-Down
All ADCs and DACs of the AK4613 are placed in power-down mode by bringing the PDN pin “L” which resets both
digital filters at the same time. The PDN pin “L” also resets the control registers to their default values. In power-down
mode, when the DVMPD pin “L”, the analog outputs go to VCOM voltage, when the DVMPD pin =“H”, the analog
outputs go to Hi-Z. The SDTO1-2, DZF1-2 pins go to “L” in the power-down mode. This reset should always be executed
after power-up. For the ADC, an analog initialization cycle (518/fs) starts 3~4/fs after exiting power-down mode. The
output data, SDTO1-2, is available after 521~522 cycles of the LRCK clock. For the DAC, an analog initialization cycle
(516/fs) starts 3~4/fs after exiting power-down mode. The analog outputs are VCOM voltage when the DVMPD =pin
“L”, and the analog outputs go to Hi-Z when the DVMPD pin =“H” during the initialization. Figure 44 shows the
power-down and power-up sequences.
Power
PDN
(12)
ADC Internal
State
DAC Internal
State
(10)
3~4/fs
(1)
518/fs
Init Cycle
516/fs (2)
Init Cycle
ADC In
(Analog)
ADC Out
“0”data (4)
(6)
(Digital)
DAC In
(Digital)
“0”data
DAC Out
(5)
(Analog)
Clock In
Don’t care
MCLK,LRCK,SCLK
DZF1/DZF2
External
Mute
(7)
10~11/fs(11)
Mute ON ⁽⁹⁾
Normal Operation
Power-down
Normal Operation
GD ⁽³⁾
Power-down
GD
GD(3)
“0”data
“0”data
GD
(7)
(7)
Don’t care
(7)
Don’t care
Mute ON
Notes:
(1) The analog part of ADC is initialized after exiting power-down state.
(2) The analog part of DAC is initialized after exiting power-down state.
(3) Digital output corresponds to analog input and analog output corresponds to digital input have group delay (GD).
(4) ADC output is “0” data at power-down state.
(5) The analog outputs are VCOM voltage when the DVMPD pin “L”, and the analog outputs go to Hi-Z when the
DVMPD pin “H” in power-down mode.
(6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise
influences system applications.
(7) Click noise occurs at the falling edge of PDN and at 519~520/fs after the rising edge of the PDN pin.
(8) DZF1-2 pins are “L” in power-down mode (PDN pin = “L”).
(9) Please mute the analog output externally if the click noise (7) influences system applications.
(10) There is a delay, 3~4/fs from PDN pin “H” to the start of initial cycle.
(11) DZF pin= “L” for 10∼11/fs after PDN pin = “↑”.
(12) The PDN pin must be “L” when power up the AK4613 and set to “H” after all powers are supplied.
Figure 44. Pin power-down/Pin power-up sequence example
MS1052-E-02
- 46 -
2010/03