AK5730 Datasheet, PDF (46/50 Pages) Asahi Kasei Microsystems – 4-Channel Differential Audio ADC for Line & Mic Inputs

[AK5730]
Addr
16H
17H
18H
19H
1AH
1BH
Register Name
SAR Thresh A High byte
SAR Thresh A Low byte
SAR Thresh B High byte
SAR Thresh B Low byte
SAR Thresh C High byte
SAR Thresh C Low byte
R/W
Default
D7
THA12
THA04
THB12
THB04
THC12
THC04
R/W
0
D6
THA11
THA03
THB11
THB03
THC11
THC03
R/W
0
D5
THA10
THA02
THB10
THB02
THC10
THC02
R/W
0
D4
THA09
THA01
THB09
THB01
THC09
THC01
R/W
0
D3
THA08
0
THB08
0
THC08
0
R/W
0
D2
THA07
0
THB07
0
THC07
0
R/W
0
D1
THA06
0
THB06
0
THC06
0
R/W
0
D0
THA05
0
THB05
0
THC05
0
R/W
0
SAR Raw Data Threshold A/B/C.
A: R2/(2R1+R2)*Vbias:Pos. and neg. inputs shorted in LINE and Phone mode.
B: (R2+R3)/(R1+R2+R3)*Vbias: Input open in Booster input mode.
C: R2/(R1+R2+R3)*Vbias: Input open in Booster input mode.
Addr
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
Register Name
SAR IN1+ High byte
SAR IN1+ Low byte
SAR IN1- High byte
SAR IN1- Low byte
SAR IN2+ High byte
SAR IN2+ Low byte
SAR IN2- High byte
SAR IN2- Low byte
SAR IN3+ High byte
SAR IN3+ Low byte
SAR IN3- High byte
SAR IN3- Low byte
SAR IN4+ High byte
SAR IN4+ Low byte
SAR IN4- High byte
SAR IN4- Low byte
SAR VBAT High byte
SAR VBAT Low byte
R/W
Default
D7
1P12
1P04
1N12
1N04
2P12
2P04
2N12
2N04
3P12
3P04
3N12
3N04
4P12
4P04
4N12
4N04
VB12
VB04
RD
0
D6
1P11
1P03
1N11
1N03
2P11
2P03
2N11
2N03
3P11
3P03
1N11
3N03
4P11
4P03
4N11
4N03
VB11
VB03
RD
0
D5
1P10
1P02
1N10
1N02
2P10
2P02
2N10
2N02
3P10
3P02
3N10
3N02
4P10
4P02
2N10
4N02
VB10
VB02
RD
0
D4
1P09
1P01
1P09
1N01
2P09
2P01
2N09
2N01
3P09
3P01
3P09
3N01
4P09
4P01
4N09
4N01
VB09
VB01
RD
0
D3
1P08
0
1N08
0
2P08
0
2N08
0
3P08
0
3N08
0
4P08
0
4N08
0
VB08
0
RD
0
D2
1P07
0
1N07
0
2P07
0
2N07
0
3P07
0
3N07
0
4P07
0
4N07
0
VB07
0
RD
0
D1
1P06
0
1N06
0
2P06
0
2N06
0
3P06
0
3N06
0
4P06
0
4N06
0
VB06
0
RD
0
D0
1P05
0
1N05
0
2P05
0
2N05
0
3P05
0
3N05
0
4P05
0
4N05
0
VB05
0
RD
0
SAR Raw Data Readout.
When reading these registers, always read the high byte first. The low byte is only updated when the high byte is read.
This ensures that the values read from the two registers come from the same 12-bit word.
Rev 0.8
- 46 -
2013/06