AK5730 Datasheet, PDF (20/50 Pages) Asahi Kasei Microsystems – 4-Channel Differential Audio ADC for Line & Mic Inputs

[AK5730]
OPERATION OVERVIEW
■ System Clock
The MSN pin selects either master or slave mode. MSN pin = “H” selects master mode and “L” selects slave mode.
In slave mode, MCLK, LRCK(fs) and BICK are required to operate the AK5730. MCLK should be synchronized with
LRCK but the phase is not critical. Table 1 shows the relationship between the sampling rate and the frequencies of
MCLK and BICK. The sampling speed is set by FS0 and FS1 bits (Table 3).
After exiting reset at power-up in slave mode, the AK5730 is in power-down mode until MCLK and LRCK and BICK are
input.
In master mode, only MCLK is required. Master Clock Input Frequency should be set with the CKS1-0 bits (Table 2), and
the sampling speed should be set by the FS1-0 bits. After exiting reset at power-up in slave mode, the AK5730 is in
power-down mode until MCLK are input.
LRCK
fs
8kHz
32kHz
44.1kHz
48kHz
256fs
2.048
8.192
11.2896
12.288
MCLK (MHz)
384fs
3.072
12.288
16.9344
18.432
512fs
4.096
16.384
22.5792
24.576
BICK (MHz)
64fs
0.512
2.048
2.8224
3.072
Table 1. System Clock Example
CKS1 bit CKS0 bit
Clock Speed
0
0
256fs
0
1
384fs
1
0
512fs
(default)
1
1
(reserved)
Table 2. Master Clock Control (Master Mode)
FS1 bit
0
0
1
1
FS0 bit
Sampling Rate
0
24kHz – 48kHz
1
12kHz – 24kHz
0
8kHz – 12kHz
1
8kHz – 12kHz (reserved)
Table 3. Sampling Rate (fs)
(default)
Rev 0.8
- 20 -
2013/06