AK5730 Datasheet, PDF (21/50 Pages) Asahi Kasei Microsystems – 4-Channel Differential Audio ADC for Line & Mic Inputs

[AK5730]
■ Master Mode and Slave Mode
Master Mode and Slave Mode are selected by setting the M/S pin. (“H”=Master Mode, “L”=Slave Mode)
In master mode (M/S pin= “H”), LRCK pin and BICK pin are output pins.
In slave mode (M/S pin= “L”), LRCK pin and BICK pins are input pins
PLL1/0 bits control the PLL modes which generates the internal MCLK from BICK.
Master clock should be input the 512fs in Master mode and BICK 512fs Output PLL mode. (PLL1/0 bits = “11”)
PDN
L
L
H
H
H
H
H
M/S pin
L
H
L
L
L
L
H
PLL1 bit
*
*
0
0
1
1
*
PLL0 bit
*
*
0
1
0
1
*
LRCK pin
Input
“L” Output
Input
Input
Input
Input
Output
Table 4. LRCK and BICK pins
BICK pin
Input
“L” Output
Input (PLL off)
64fs Input (PLL mode)
256fs Input (PLL mode)
512fs Input (PLL mode)
Output
(*: Don’t Care)
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz
and scales with the sampling rate (fs).
HPF are controlled by the HPE4-1 bits.
HPE1 bit
L
H
HPF
ADC1 HPF off
ADC1 HPF on
(default)
HPE2 bit
L
H
HPF
ADC2 HPF off
ADC2 HPF on
(default)
HPE3 bit
L
H
HPF
ADC3 HPF off
ADC3 HPF on
(default)
HPE4 bit
L
H
HPF
ADC4 HPF off
ADC4 HPF on
(default)
Table 5. HPF Operation Setting
Rev 0.8
- 21 -
2013/06