AK5730 Datasheet, PDF (35/50 Pages) Asahi Kasei Microsystems – 4-Channel Differential Audio ADC for Line & Mic Inputs

[AK5730]
■ Power Up/Down Sequence
The each block of the AK5730 is placed in power-down mode by bringing the PDN pin to “L” and both digital filters are
reset at the same time. The PDN pin =“L” also resets the control registers to their default values. In power-down mode, the
SDTO pin goes to “L”. This reset must always be executed after power-up.
In slave mode, after exiting reset at power-up and etc., the ADC starts operation from the rising edge of LRCK after
MLCK inputs. The AK5730 is in power-down mode until MCLK and LRCK and BICK are input.
The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 1041/fs cycles of LRCK clock. Figure 34 shows the sequences of the power-down and the
power-up.
When RSTN bit = “0”, all circuits are powered-down but the internal register are not initialized.
Power
PDN pin
(1) (2)
PLL
VP pin
2VP pin
(3)
Normal Operation
(6)
VDD
1.67 x VDD
(1.67 x VDD) x2
VDD
VDD
(9)
VDD
(9)
MICREF pin
MICPWR pin
0V
(4)
ADC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
“0”data (5)
VDD
(7) 1041/fs
Init Cycle
Normal Operation
0V
Normal Operation
Power-down
(8)
GD
GD
“0”data
Clock In
Don’t care
MCLK,LRCK,BICK
Don’t care
Figure 34 Power-up/down Sequence Example
Rev 0.8
- 35 -
2013/06